1. Field of the Invention
The present invention relates to a test circuit and, more particularly, to a test circuit including a TAP (Test Access Port) controller defined in IEEE 1149.
2. Description of Related Art
The circuit scales of semiconductor devices have recently increased, and the number of ports for testing a semiconductor device is showing a tendency to increase. If the number of ports increases, then a package becomes larger, which leads to the difficulty in size reduction. There is thus a call for a reduction in the number of ports. Under the circumstances, the IEEE (Institute of Electrical and Electronics Engineers) has established IEEE 1149 in order to reduce the number of test ports. According to IEEE 1149.1, which is a part of IEEE 1149, it is possible to test a semiconductor device using five ports and a TAP controller.
The five ports are referred to as a TDI port, a TRST port, a TCK port, a TMS port, and a TDO port, respectively. In the following description, one set of the TDI port, the TRST port, the TCK port, the TMS port, and the TDO port will be referred to as a group of test ports. The TAP controller includes a state machine, an instruction register, and a boundary scan register. The instruction register stores a control code for TAP controller, which is inputted from the TDI port. The boundary scan register stores a test pattern which is inputted from the TDI port. The state machine controls the operating state of the TAP controller on the basis of a TMS signal which is inputted from the TMS port.
If there are a plurality of circuits as a test target, then a plurality of TAP controllers are used according to the number of circuits to be tested. If there are a plurality of circuits to be tested, then the circuits to be tested may operate individually or a plurality of test blocks may operate in cooperation. Accordingly, if a plurality of TAP controllers are used, then the connection among boundary scan registers of the plurality of TAP controllers is changed according to the operation of circuits to be tested.
For example, the test circuits described in Patent Document 1, Patent Document 2, and Patent Document 3 are each capable of selecting which one of TAP controllers provided for respective circuits to be tested is to be actuated. With this configuration, the test circuits can perform an individual test only on one arbitrarily selected circuit to be tested. However, the test circuits described in Patent Documents 1 to 3 suffer from the problem of inability to switch a unit for circuits to be tested included in testing. To cope with this problem, Patent Document 4 discloses a test circuit capable of switching a unit for circuits for a test target included in testing.
The test circuit described in Patent Document 4 includes selection circuits in one TAP controller. The selection circuits are arranged to divide a plurality of boundary scan registers into groups. Each selection circuit switches between transmitting, to boundary scan registers connected at a subsequent stage, a test pattern which is transmitted through boundary scan registers connected at a previous stage and transmitting, to the boundary scan registers connected at the subsequent stage, the test pattern which is transmitted through a path bypassing the boundary scan registers connected at the previous stage. With this configuration, the test circuit described in Patent Document 4 can adjust the length of a boundary scan chain composed of boundary scan registers according to the length of a test pattern. Since the test circuit described in Patent Document 4 has a circuit to be tested provided for each of scan chains divided by the selection circuits, the test circuit can change the number of circuits to be tested which can be tested using one test pattern.
The test circuit disclosed in Patent Document 5 has boundary scan chains connected in parallel and a converter which outputs a digital value on the basis of the voltage value of a multilevel signal (analog signal) inputted from the outside. The converter outputs a digital value to each of the boundary scan chains when one multilevel signal is inputted. With this configuration, the test circuit disclosed in Patent Document 5 shortens the time required for a test pattern to be inputted or outputted from or to each boundary scan chain.
[Patent Document 1] Japanese Patent Laid-Open No. 2004-164367
[Patent Document 2] Japanese Patent Laid-Open No. 2007-148754
[Patent Document 3] Japanese Patent Laid-Open No. 2007-271390
[Patent Document 4] Japanese Patent Laid-Open No. 2001-203322
[Patent Document 5] Japanese Patent Laid-Open No. 2006-189305